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? semiconductor components industries, llc, 2010 january, 2010 ? rev. 2 1 publication order number: NCP5030/d NCP5030 buck-boost converter to drive a single led from 1 li-ion or 3 alkaline batteries the NCP5030 is a fixed frequency pwm buck ? boost converter optimized for constant current applications such as driving high ? powered white led. the buck ? boost is implemented in an h ? bridge topology and has an adaptive architecture where it operates in one of three modes: boost, buck ? boost, or buck depending on the input and output voltage condition. this device has been designed with high ? efficiency for use in portable applications and is capable of driving in dc up to 900 ma into a high power led for flashlight / torch applications. to protect the device cycle ? by ? cycle current limiting and a thermal shutdown circuit have been incorporated as well as output over ? voltage protection. the 700 khz switching frequency allows the use of a low value 4.7 h and ceramic capacitors. the NCP5030 is housed in a low profile space efficient 3x4 mm thermally enhanced wdfn. features ? efficiency: 87% at 500 ma and 3.3 v v in ? internal synchronous rectifier, no schottky diodes ? adjustable switching limit current to optimize inductor size ? 0.3 a shut ? down control with ?true ? cut off? ? input voltage range from 2.7 v to 5.5 v ? 200 mv feedback voltage ? output over ? voltage and thermal shut down protection typical applications ? portable flashlight / torch lights figure 1. typical application circuit l1: tdk rlf7030t ? 4r7m3r4 c1: 1 f 6.3 v x5r c2: 10 f 3.6 v 0805 tdk: c2012x5r0j106mt c3: 22 f 6.3 v x5r tdk: c2012x5r0j226mtj vin cin 1 f 1 cell li ? ion 2.7 to 5.5 c2 10 f 4.7 h l1 pvin vin lx1 lx1 lx2 vout vs NCP5030 pgnd fb comp agnd ctrl enable 39 k r2 100 k 330 pf 22 pf pca c5 c4 r sense r3 220 m r1 c in c out c3 22 f d1 5030 = specific device code a = assembly location y = year ww = work week = pb ? free package (note: microdot may be in either location) wdfn12 3x4 mt suffix case 506ay marking diagram http://onsemi.com 5030 ayww 1 pin connections (top view) 13 12 11 10 9 8 7 1 2 3 4 5 6 pca agnd vin vs vout lx2 fb comp ctrl pvin lx1 lx1 exposed pad (pin 13) is pgnd must be soldered to pcb gnd plane 1 12 see detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet. ordering information
NCP5030 http://onsemi.com 2 100 95 90 85 80 75 70 65 60 55 50 2.5 3.0 3.5 4.0 4.5 5.0 5.5 efficiency (%) v in (v) i out = 300 ma figure 2. efficiency vs. v in voltage pwm controller 12 pca ctrl 250 k bandgap 11 3 1 2 agnd fb comp pgnd osc 700 khz thermal shutdown 10 4 5/6 7 vin pvin lx1 lx2 13 8 9 vout vs figure 3. simplified block diagram r1 39 k 200 mv up to 900 ma led c3 r3 220 m c4 22 pf c5 330 pf r2 100 k 22 f x5r 1206 6.3 v c2 4.7 h l1 c1 1 f v bat 10 f x5r 0805 6.3 v
NCP5030 http://onsemi.com 3 pin function description pin name type description 1 fb input feedback: reference voltage is 200 mv. the cathode of the led and a resistor to ground to set the led current should be connected at this point. a 5% metal film resistor, or better, is recommended for best output accuracy. an analog signal can be applied to this input to dim the led. 2 comp input loop compensation: a frequency compensation network must be connected between this pin to the ground to ensure the stability of the closed loop. see ?loop compensation? guidelines. 3 ctrl input control and enable: an active high logic level on this pin enables the device. a built ? in pulldown resistor disables the device if the input is left open. this pin can also be used to control the average current into the load by applying a low frequency pwm signal. if a pwm signal is applied, the frequency should be high enough to avoid optical flicker, but be no greater than 1.0 khz. 4 pvin power power voltage input supply: a 10 f ceramic capacitor or larger must bypass this input to the ground. this capacitor should be placed as close a possible to this input. 5/6 lx1 power switch lx1: both pins are connected to the input node of the h ? bridge. the inductor should be connected between this node and lx2. the recommended inductor size is 4.7 h. 7 lx2 power switch lx2: this pin is connected to the opposite node of the h ? bridge and the power inductor is connected between this node and lx1. 8 vout power power output: a filter capacitor is necessary on this pin for the stability of the loop, to smooth the current flowing into the load, and to limit the noise created by the fast transients present in this circuitry. a 22 f ceramic capacitor bypass to gnd or larger is recommended. for white led applications, this pin is also connected to the anode of the led. care must be observed to avoid emi through the pcb copper tracks connected to this pin. 9 vs power voltage sense: this pin must be connected to c out with a dedicated track to minimize serial parasitic inductor and to sense v out with high accuracy. this pin supplies some of the NCP5030 internal blocks when the voltage is higher than v in . 10 vin power supply pin: this pin supplies the internal control circuitry and must be connected to pvin. recommended bypass capacitor is 1.0 f ceramic or larger. 11 agnd power analog ground: this pin is the system ground and carries the analog signals. this pin must be connected to the ground plan like pgnd. 12 pca input peak current adjust: a resistor between this input and ground controls the maximum peak current allowed in the inductor. the minimum value for this resistor is 30 k . increasing this value decreases the peak current. this allows the user to adjust the current based on the application needs and scale the size of the inductor accordingly. see ?switch current limit?guidelines in application section. 13 pgnd power power ground: this pin is the power ground for NCP5030 and carries the switching current. care must be observed to avoid high ? density current flow in a limited pcb copper track.
NCP5030 http://onsemi.com 4 maximum ratings (note 1) rating symbol value unit power supply voltage (note 2) v bat 7.0 v over v oltage protection v out 6.5 v human body model (hbm) esd rating (note 3) esd hbm 2.0 kv machine model (mm) esd rating (note 3) esd mm 200 v digital input v oltage digital input current ctrl ? 0.3 < v in < v bat + 0.3 1.0 v ma wdfn 3x4 package power dissipation @ t a = +85 c (note 5) thermal resistance, junction ? to ? case thermal resistance, junction ? to ? air p d r jc r ja internally limited 6.0 (note 6) w c/w c/w operating ambient temperature range t a ? 40 to +85 c operating junction temperature range t j ? 40 to +125 c maximum junction t emperature t jmax +150 c storage temperature range t stg ? 65 to +150 c moisture sensitivy level (note 7) msl 1 stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. maximum electrical ratings are defined as those values beyond which damage to the device may occur at t a = 25 c. 2. according to jedec standard jesd22 ? a108b . 3. this device series contains esd protection and passes the following tests : human body model (hbm) 2.0 kv per jedec standard: jesd22 ? a114 for all pins machine model (mm) 200 v per jedec standard: jesd22 ? a115 for all pins 4. latchup current maximum rating: 100 ma per jedec standard: jesd78. 5. the thermal shutdown set to 160 c (typical) avoids irreversible damage on the device due to power dissipation. 6. for the 12 ? pin 3x4 wdfn package, the r ja is highly dependent on the pcb heat ? sink area. for example, r ja can be 57 c/w for a one layer board and 43 for a four layer board. 7. per ipc/jedec standard: j ? std ? 020a.
NCP5030 http://onsemi.com 5 electrical characteristics ( limits apply for t a between ? 40 c to +85 c and v in = 3.6 v unless otherwise noted.) characteristic symbol min typ max unit operational power supply v in 2.7 ? 5.5 v maximum inductor current (note 11) (see figure 8) i peak_max ? 20% 4.0 +20% a switches p1 and p2 on resistance p mos r dson ? 100 ? m switches n1 and n2 on resistance n mos r dson ? 100 ? m switches p1 and p2 leakage current p mos l ? 0.5 ? a switches n1 and n2 leakage current n mos l ? 0.5 ? a internal oscillator frequency (note 8) f osc 600 700 800 khz efficiency (notes 9, 10 and 11) e ff ? 85 ? % output voltage range (note 11) v out 2.2 ? 5.5 v v out ? v in threshold to change mode from boost to buck ? boost t boost ? 375 ? mv v in ? v out threshold to change mode from buck ? boost to buck t buck ? 650 ? mv threshold to change mode hysteresis h mode ? 100 ? mv available output power (note 11) when v in 3.1 v (v out = 4.7 v, 900 ma) p out 4.3 ? ? w feedback voltage threshold in steady state at 25 c f bv 190 200 210 mv line regulation, measured on fb pin (note 8) from dc to 100 hz and r fb = 1 f bvlr ? 5.0 ? mv/v feedback input current f bc ? ? 0.1 a standby current at i out = 0 ma, ctrl = low, v bat = 4.2 v i stb ? 0.3 3.0 a quiescent current switching at i out = 0 ma, ctrl = high, v bat = 4.2 v (note 12) i qs ? 5.0 ? ma v in undervoltage lockout threshold to enable the converter u vlo 2.2 2.4 2.6 v undervoltage lockout hysteresis u vloh ? 100 ? mv soft ? start time (note 11) s st ? 1000 ? s limit of ctrl pin pwm dimming frequency (note 11) f dim ? 0.2 ? khz thermal shutdown protection t sd ? 160 ? c thermal shutdown protection hysteresis t sdh ? 20 ? c voltage input logic low v il ? ? 0.4 v voltage input logic high v ih 1.2 ? ? v ctrl pin pulldown resistance r ctrl 150 220 290 k 8. t a between ? 10 c to +85 c 9. efficiency is defined by 100 * (p out /p in ) at 25 c. v in = 3.3 v, i out = 500 ma, load = 1 led (v f = 3.9 v) 10. l = 4.7 h (tdk rlf7030t ? 4r7m3r4), c out = 22 f x5r 11. guaranteed by design and characterized. 12. the overall tolerance is dependent on the accuracy of the external resistor.
NCP5030 http://onsemi.com 6 typical performance characteristics figure 4. efficiency vs. v in led = lumileds luxeon iii, l = tdk rlf7030t ? 4r7 v in (v) 5.5 5.0 4.5 4.0 3.5 3.0 2.5 50 55 60 70 80 85 95 100 figure 5. buck mode efficiency vs. i out @ v out = 3.1 v l = tdk rlf7030t ? 4r7 figure 6. buck ? boost mode eff. vs. i out @ v out = 3.8 v l = tdk rlf7030t ? 4r7 i out (ma) i out (ma) 900 700 800 600 400 200 0 50 60 70 80 90 100 900 700 800 600 400 200 0 50 60 70 80 90 100 figure 7. boost mode efficiency vs. i out @ v out = 5.0 v l = tdk rlf7030t ? 4r7 figure 8. i peak_max vs. r pca i out (ma) r pca (k ) 900 700 800 600 400 200 0 50 60 70 80 90 100 1000 100 10 0 0.5 1.0 1.5 2.5 3.0 3.5 4.0 eff (%) eff (%) eff (%) eff (%) i peak(max) (a) 65 75 90 efficiency = 100 x (p led /p in ) 100 ma 400 ma 900 ma v in = 5.5 v v in = 4.5 v v in = 3.9 v v in = 4.0 v v in = 4.4 v v in = 3.4 v v in = 3.6 v v in = 3.1 v v in = 4.1 v v in = 3.6 v 2.0 500 300 100 500 300 100 500 300 100
NCP5030 http://onsemi.com 7 typical performance characteristics figure 9. nmos r dson vs. temperature figure 10. pmos r dson vs. temperature temperature ( c) temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 50 100 150 100 80 60 40 20 0 ? 20 ? 40 50 100 150 figure 11. transitional period switch pins (lx1 and lx2) from boost to buck ? boost when v out ? v in is < than 375 mv figure 12. transitional period switch pins (lx1 and lx2) from buck to buck ? boost when v in ? v out is > than 650 mv figure 13. oscillator frequency vs. temperature v out = 3.6 v, v in = 3.6 v figure 14. feedback voltage vs. temperature v out = 3.6 v, v in = 3.6 v temperature ( c) temperature ( c) 125 100 50 25 0 ? 25 ? 50 600 610 620 630 640 660 670 680 100 80 60 40 20 0 ? 20 ? 40 190 195 200 205 210 (m ) (m ) frequency (khz) feedback voltage v in = 4.2 v v in = 3.1 v v in = 2.7 v v in = 3.6 v v in = 4.2 v v in = 3.1 v v in = 2.7 v v in = 3.6 v 75 650 690 710 720 730 700
NCP5030 http://onsemi.com 8 detailed operating description enable 220 k ctrl 3 pgnd 1.18 v uvlo one shot i_sense ipeak comp + ? disable vin thermal protection pwm sense current + ? i_pmax osc 700 khz mode detection 220 m r_sense d1 and anticross ? conduction i_sense comp agnd 2 bandgap and current sources 39 k rpca sense pca vin ovp vs fb 1 ovp ref ovp comp + ? 1000 mv exposed pad clock 22 pf 100 k 330 pf ipeak_ref ramp comp + ? pwm comp 5/6 7 10 lx2 soft start vin vs 9 p1 n2 n1 p2 pvin 200 mv lx1 4 constant toff 300 ns 2.7 to 5.5 v + ? vin uvlo comp error amp uvlo ref logic figure 15. functional block diagram 4.7 h 30 m v bat c in 10 f rst c out 22 f v out set reference 12 8 13 11
NCP5030 http://onsemi.com 9 operation the NCP5030 dc ? dc converter is based on a current mode pwm architecture specifically designed to efficiently provide a regulated current to a high current white led. this device utilizes fixed frequency synchronous buck ? boost switching regulator architecture. this topology is critical in single cell lithium ? ion/ polymer battery or 3 alkaline powered applications as the forward voltage of the led may be greater than or less than the battery voltage. a low feedback voltage of 200 mv (nom) minimizes power losses in the current setting resistor connected between the cathode of the led and ground. the core switching regulator is configured as a full bridge with four low r dson (0.1 ) mosfet switches to maximize efficient power delivery. another advantage of this topology is that it supports a true ? shut down mode where the led will be disconnected from the power supply when the device is placed in disable mode. figure 16 shows how the four switches are connected to charge and discharge the current from p vin to v out through the inductor. load l lx1 n1 lx2 n2 p1 p2 figure 16. basic power switches topology v out i out v in i in c out the converter operates in three different modes as a function of v out ? v in (figure 17): in buck mode when v out is below v in ? 650 mv (t buck nominal), in boost mode when v out is above v in + 375 mv (t boost nominal) and in buck ? boost mode when v out is between this tow thresholds. buck 2 ? phase buck ? boost boost 2 ? phase 3 ? phase figure 17. conversion mode v out v in t buck t boost the internal oscillator provides a 700 khz clock signal to trigger the pwm controller on each rising edge (set signal) which starts a cycle. in pure buck or boost mode, the converter operates in two ? phase mode, the first one to charge the inductor, followed by a synchronous rectifier discharge phase. however, in buck ? boost mode, to get high efficiency the converter controls the switches in three separate phases (see buck ? boost mode section). the capacitor c out is used to store ener gy from the inductor to smooth output voltage thus constantly powering the load. buck mode (v out < v in ? 650 mv) in buck mode, switches p1 and n1 are toggling and the two others are fixed, the switch n2 is all time off and the switch p2 is all time on. the buck converter operates in two separate phase (see figure 18). the first one is t on when i in = i out . during this phase the switch p1 is on, n1 is off and the current increases through the inductor. the switch current is measured by the sense current and added to the ramp comp signal. then pwm comp compares the output of the adder and the signal from error amp. when the comparator threshold is exceeded, t on phase is followed by t off . p1 switch is turned off and n1 is on until next clock rising edge. the current is only delivered by the inductor, which means that i in =0 lx1 lx2 start cycle 1.43 s figure 18. basic dc ? dc buck operation lx2 = v out t on t off i valley i peak i out i l boost mode (v out > v in + 375 mv) the switches in boost mode are inversely controlled than in buck mode. switches p2 and n2 are toggling and the two others are fixed. switch p1 is all time on and the switch n1 is all time off. the boost converter operates in two separate phases (see figure 19 ). the first one is t on when
NCP5030 http://onsemi.com 10 the inductor is charged by current from the battery to store up energy. during this phase the switch n2 is on and p2 is off. the switch current is measured by the sense current and added to the ramp comp signal. then pwm comp compares the output of the adder and the signal from error amp. when the comparator threshold is exceeded, the flip ? flop circuit is reset, p2 switch is turned on, and n2 is off until the rising edge of the next clock cycle. lx1 lx2 1.43 s start cycle figure 19. basic dc ? dc boost operation lx1 = v in i out i l t on t off i valley i peak buck ? boost mode (v in ? 650 mv < v out < v in + 375 mv) figure 20 shows the basic dc ? dc buck ? boost operation. now, all four switches are running and the controller operates in three separate phases to reach higher efficiency. the first step is t on when the inductor is charged by current from the battery. during this phase the switch p1_n2 are on and p2_n1 are off. like the other modes, the current measured by sense current is added to the ramp comp signal and compared by pwm comp with the signal from error amp. when pwm comp threshold is exceeded, the flip ? flop circuit is reset and the controller switches in t off phase. in this second phase, the switch p1_n2 are off and p2_n1 are on. because time of t off phase is constant, the current stored in the inductor during 250 ns (nominal) is drained to v out . after this, const ant t off delay is over, the circuit logic switches in the third phase named tc (time conduction) where the inductor is directly connected from pvin to v out . the switch p1_p2 are on and switches n_n2 are off until the rising edge of the next clock cycle. lx1 lx2 1.43 s start cycle figure 20. basic dc ? dc bb operation i out i l t on t off t c v in v out i peak i valley in addition, there are four safety circuits like ovp, uvlo, ipeak comp, thermal protection, which can disable the dc ? dc conversion. error amp and compensation regulation loop is closed by the error amplifier, which compares the feedback voltage with the reference set at 200 mv. thanks to the transconductance structure, the compensation network is directly connected to the error amplifier output. this external passive network is necessary to sets the dominant pole to gets a good loop stability. the compensation network shown in figure 21 provides a phase margin greater than 45 whatever the current drives in a white led load. comp 22 pf 100 k 330 pf figure 21. compensation network led current selection the feedback resistor (r sense ) determines the led current in steady state. the control loop regulates the current in such a way that the average voltage at the fb input is 200 mv (nominal). for example, should one need 800 ma output current, r sense should be selected according to the following equation: r sense f bv i led 200 mv 800 ma 250 m (eq. 1)
NCP5030 http://onsemi.com 11 current selection figure 22 shows an application schematic to drive two selected currents i 1 and i 2 . i led i 1 i 2 (eq. 2) 200 mv r1 m1 nths5404 r2 led fb pgnd NCP5030 figure 22. two current selections r sense v out v s flash/torch i 1 i 2 an active low logic level of m1 enables the low current mode, so i 2 = 0 and i 1 = i led = 200 mv / r 1 . for example, should one need 200 ma for low current mode and 800 ma for high current mode, r 1 should be selected according to the following below: r 1 f bv i 1 200 mv 200 ma 1.0 (eq. 3) so an active high logic level m1 on gate enables the high current mode then i flash = i 1 + i 2 and according equation 2 and 3, r2 should be selected regarding the following equation: r 2 f bv i flash i 1 r dson_m1 (eq. 4) r 2 200 mv 800 ma 200 ma 33 m r 2 300 m some recommended resistors include, but are not limited to: panasonic erj3bqf1r0v (1.0 1% 0603) panasonic erj3bqfr30v (300 m 1% 0603) panasonic erj3bqj1r0v (1.0 5% 0603) panasonic erj3bqjr30v (300 m 5% 0603) analogue dimming in white led applications, it is desirable to operate the leds at a specific operating current, as the color shift as the bias current. as a consequence, it is recommended to dim the led current by pulse width modulation techniques. a low frequency pwm signal can be applied to the ctrl input. led brightness can be changed by varying the duty cycle. to avoid any optical flicker the frequency must be higher than 100 hz and preferably less than 300 hz. because of the soft ? start function set at 1000 s (nominal), higher frequency would cause the device to remain active with lower than expected brightness. nevertheless, in this case a dimming control using a filtered pwm signal can be used. in addition, for dc voltage control the same technique is suitable and the filter is taken away. please refer to ?npc5030 dimming control application note?. inductor selection three main electrical parameters need to be considered when choosing an inductor: the value of the inductor, the saturation current and the dcr. firstly, we need to check if the inductor is able to handle the peak current without saturating. therefore, we have to consider that the maximum peak inductor current is in buck ? boost mode when v out is closed t boost threshold for the lower operating v in . obviously, the peak current inductor is higher when this device supplies the maximum required current. in this case, the dc ? dc converter is supposed to operate in continuous conduction mode (ccm) so the dotted curve in figure 23 gives the inductor peak current as a function of load current: figure 23. inductor peak currents vs. i out (ma) i out (ma) 900 700 800 600 400 200 0 0.5 1 1.5 2 2.5 i peak (a) switch current limit setup by r pca 500 300 100 operating inductor peak current finally, an acceptable dcr must be selected regarding losses in the coil and must be lower than 100 m to limit excessive voltage drop. in addition, as dcr is reduced, overall efficiency will improve. some recommended inductors are included but are not limited to: tdk vlf5014at ? 4r71r1 tdk rlf7030t ? 4r7m3r4 copper bussmann fp3 ? 4r7 murata lqh43cn4r7m03l nic: nip16w4r7mtrf switch current limit this safety feature is clamping the maximum allowed current in the inductor according to external r pca resistor, which is connected between pca input and the ground. this allows the user to reduce the peak current being drawn
NCP5030 http://onsemi.com 12 from the supply according to the application?s specific requirements. the i peak maximum value is 4 a, resulting in a minimum resistor value of 30 k . please refer to figure 8 i peak_max vs r pca page 6 to choose r pca value versus i peak_max . by limiting the peak current to the needs of the application, the inductor sizing can be scaled appropriately to the specific requirements. this allows the pcb footprint to be minimized. input and output capacitors selection c out stores energy during the t off phase and sustains the load current during the t on phase. in order ensure the loop stability and minimize the output ripple, at least 22 f low esr multi ? layer ceramic capacitor type x5r is recommended. the v in and pv in input pin need to be bypassed by a x5r or an equivalent low esr ceramic capacitor. near the pv in pin at least 10 f 6.3 v or higher ceramic capacitor is needed. regarding v in pin a 1 f 6.3 v close to the pad is sufficient. some recommended capacitors include but are not limited to: 22 f 6.3 v 0805 tdk: c2012x5r0j226mtj 22 f 6.3 v 1206 murata: grm31cr60j226ke19l 10 f 6.3 v 0805 tdk c2012x5r0j106mt over voltage protection (ovp) the NCP5030 regulates the load current. if there is an open load condition such as a lost connection to the white led, the converter keeps supplying current to the cout capacitor causing the output voltage to rise rapidly. to prevent the device from being damaged and to eliminate external protection components such as zener diode, the NCP5030 incorporates an ovp circuit, which monitors the output voltage with a resistive divider network and a comparator and voltage reference. if the output reaches 6 v (nominal), the ovp circuit will detect a fault and inhibit pwm operation. this comparator has 200 mv hysteresis to allow the pwm operation to resume automatically when the load is reconnected and when the voltage drops below 5.8 v. under voltage lock out to ensure proper operation under low input voltage conditions, the device has a built ? in under ? voltage lock out (uvlo) circuit. the device remains disabled until the input voltage exceeds 2.35 v (nominal). this circuit has 100 mv hysteresis to provide noise immunity to transient conditions. thermal protection normal operation of the NCP5030 is disabled to protect the device if the junction temperature exceeds 160 c. when the junction temperature drops below 140 c, normal operation will resume. layout recommendations as with all switching dc/dc converter, care must be observed to the pcb board layout and component placement. to prevent electromagnetic interference (emi) problems and reduce voltage ripple of the device any copper trace, which see high frequency switching path, should be optimized. so the input and output bypass ceramic capacitor, c in and c out as depicted in figure 24 must be placed as close as possible the NCP5030 and connected directly between pins and ground plane. in additional, the track connection between the inductor and the switching input, sw pin must be minimized to reduce emi radiation. tbd figure 24. recommended pcb layout
NCP5030 http://onsemi.com 13 ordering information device package shipping ? NCP5030mttxg wdfn12, 3x4 mm (pb ? free) 3000/t ape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd801 1/d. demo board available: the NCP5030mttxgevb/d evaluation board that configures the device to drive high current through one white led.
NCP5030 http://onsemi.com 14 package dimensions wdfn12, 3x4, 0.5p case 506ay ? 01 issue b pin 1 index area a b c 0.10 c 0.10 2x 2x a c c 0.08 12x c 0.10 side view top view e2 d2 bottom view e b 12x l 16 12 7 d e a3 a1 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeter. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. dim min max millimeters a 0.70 0.80 a1 0.00 0.05 a3 0.20 ref b 0.20 0.30 d 4.00 bsc d2 3.20 3.40 e 3.00 bsc e2 1.60 1.80 e 0.50 bsc k 0.20 ??? l 0.30 0.50 0.10 b 0.05 a c c note 3 12x k 12x *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting t echniques reference manual, solderrm/d. soldering footprint* 3.30 12 x 1.75 0.55 12 x 0.30 3.35 0.50 pitch dimensions: millimeters on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, in cluding without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different a pplications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical e xperts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc prod uct could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney f ees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was neglig ent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 NCP5030/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc a sales representative

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